# munetomo-maruyama/mmRISC-2

<https://repo.masters-masters.com/en/repos/munetomo-maruyama/mmRISC-2>

[Home](https://repo.masters-masters.com/en) › [munetomo-maruyama](https://repo.masters-masters.com/en/owners/munetomo-maruyama) › [mmRISC-2](https://repo.masters-masters.com/en/repos/munetomo-maruyama/mmRISC-2)

munetomo-maruyama/mmRISC-2 has 168 stars on GitHub. Its RepoMasters card: Prototype tier. 64-bit RISC-V (RV64GC) core that boots Linux on an Arty A7 FPGA…

| Field | Value |
| --- | --- |
| Owner | [munetomo-maruyama](https://repo.masters-masters.com/en/owners/munetomo-maruyama) |
| Stars | 168 |
| Forks | 32 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | Apache-2.0 |
| Created | 2026 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [munetomo-maruyama/mmRISC-2](https://github.com/munetomo-maruyama/mmRISC-2) |

## Repository

64-bit RISC-V (RV64GC) core that boots Linux on an Arty A7 FPGA. Designed entirely by Claude Code: the specifications, RTL, verification and documents were all written by the AI.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in SystemVerilog

- [mayurkubavat/UVM-Examples · ★ 169 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/mayurkubavat/UVM-Examples)
- [riscv-verification/RVVI · ★ 168 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/riscv-verification/RVVI)
- [bsc-loca/sargantana · ★ 168 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/bsc-loca/sargantana)
- [srg320/Saturn\_MiSTer · ★ 166 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/srg320/Saturn_MiSTer)
- [gnodipac886/ViT-FPGA-TPU · ★ 165 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/gnodipac886/ViT-FPGA-TPU)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.