# myriadrf/LimeSDR-USB\_GW

<https://repo.masters-masters.com/en/repos/myriadrf/LimeSDR-USB_GW>

[Home](https://repo.masters-masters.com/en) › [myriadrf](https://repo.masters-masters.com/en/owners/myriadrf) › [LimeSDR-USB\_GW](https://repo.masters-masters.com/en/repos/myriadrf/LimeSDR-USB_GW)

myriadrf/LimeSDR-USB\_GW has 111 stars on GitHub. Its RepoMasters card: Prototype tier. Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board

| Field | Value |
| --- | --- |
| Owner | [myriadrf](https://repo.masters-masters.com/en/owners/myriadrf) |
| Stars | 111 |
| Forks | 68 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2016 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [myriadrf/LimeSDR-USB\_GW](https://github.com/myriadrf/LimeSDR-USB_GW) |

## Repository

Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by myriadrf

- [myriadrf/LimeSuite · ★ 529 · C · Alpha](https://repo.masters-masters.com/en/repos/myriadrf/LimeSuite)
- [myriadrf/LimeSDR-USB · ★ 411 · ANTLR · Alpha](https://repo.masters-masters.com/en/repos/myriadrf/LimeSDR-USB)
- [myriadrf/LoRa-SDR · ★ 276 · C++ · Alpha](https://repo.masters-masters.com/en/repos/myriadrf/LoRa-SDR)
- [myriadrf/LimeSDR-Mini · ★ 200 · ANTLR · Prototype](https://repo.masters-masters.com/en/repos/myriadrf/LimeSDR-Mini)
- [myriadrf/gr-limesdr · ★ 151 · C++ · Prototype](https://repo.masters-masters.com/en/repos/myriadrf/gr-limesdr)
- [myriadrf/LMS7002M-docs · ★ 120 · Prototype](https://repo.masters-masters.com/en/repos/myriadrf/LMS7002M-docs)

## Nearby in Verilog

- [lucysrausch/colorlight-led-cube · ★ 113 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/lucysrausch/colorlight-led-cube)
- [enjoy-digital/daisho · ★ 112 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/enjoy-digital/daisho)
- [RISC-KC/basic\_rv32s · ★ 112 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/RISC-KC/basic_rv32s)
- [JulianKemmerer/PipelineC-Graphics · ★ 110 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/JulianKemmerer/PipelineC-Graphics)
- [dawsonjon/FPGA-TX · ★ 109 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/dawsonjon/FPGA-TX)
- [zhan6841/FPGA-Accelerator-for-AES-LeNet-VGG16 · ★ 109 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/zhan6841/FPGA-Accelerator-for-AES-LeNet-VGG16)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
