# nxbyte/ARM-LEGv8

<https://repo.masters-masters.com/en/repos/nxbyte/ARM-LEGv8>

[Home](https://repo.masters-masters.com/en) › [nxbyte](https://repo.masters-masters.com/en/owners/nxbyte) › [ARM-LEGv8](https://repo.masters-masters.com/en/repos/nxbyte/ARM-LEGv8)

nxbyte/ARM-LEGv8 has 113 stars on GitHub. Its RepoMasters card: Prototype tier. Verilog Implementation of an ARM LEGv8 CPU Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [nxbyte](https://repo.masters-masters.com/en/owners/nxbyte) |
| Stars | 113 |
| Forks | 30 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2018 |
| Topics | verilog, hennessy, patterson, arm-legv8-simulator, arm, isa, pipeline-cpu, hazard-detection, forwarding-unit, single-cycle |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [nxbyte/ARM-LEGv8](https://github.com/nxbyte/ARM-LEGv8) |

## Repository

Verilog Implementation of an ARM LEGv8 CPU

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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- [nxbyte/Verilog-Projects · ★ 124 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/nxbyte/Verilog-Projects)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.