# openecos-projects/icsprout55-pdk

<https://repo.masters-masters.com/en/repos/openecos-projects/icsprout55-pdk>

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openecos-projects/icsprout55-pdk has 329 stars on GitHub. Its RepoMasters card: Alpha tier. 55nm CMOS Open Source PDK for Digital, Analog, and Mixed-Signal…

| Field | Value |
| --- | --- |
| Owner | [openecos-projects](https://repo.masters-masters.com/en/owners/openecos-projects) |
| Stars | 329 |
| Forks | 34 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2025 |
| Topics | 55nm, asic, cmos, icsprout, open-source, pdk |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [openecos-projects/icsprout55-pdk](https://github.com/openecos-projects/icsprout55-pdk) |

## Repository

55nm CMOS Open Source PDK for Digital, Analog, and Mixed-Signal Circuit Design. It supports an open-source RTL2GDS workflow for education, research, and silicon prototyping.

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## Nearby in Verilog

- [cxdzyq1110/NPU\_on\_FPGA · ★ 338 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/cxdzyq1110/NPU_on_FPGA)
- [janestreet/asic-puzzle-2026 · ★ 338 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/janestreet/asic-puzzle-2026)
- [samitbasu/rhdl · ★ 330 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/samitbasu/rhdl)
- [openasic-org/xkISP · ★ 325 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/openasic-org/xkISP)
- [lawrie/fpga\_pio · ★ 323 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/lawrie/fpga_pio)
- [JOKOSAHS/DMA-Pcileech · ★ 322 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/JOKOSAHS/DMA-Pcileech)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.