# openhwfoundation/cv32e40p

<https://repo.masters-masters.com/en/repos/openhwfoundation/cv32e40p>

[Home](https://repo.masters-masters.com/en) › [openhwfoundation](https://repo.masters-masters.com/en/owners/openhwfoundation) › [cv32e40p](https://repo.masters-masters.com/en/repos/openhwfoundation/cv32e40p)

openhwfoundation/cv32e40p has 1,319 stars on GitHub. Its RepoMasters card: Beta tier. CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY…

| Field | Value |
| --- | --- |
| Owner | [openhwfoundation](https://repo.masters-masters.com/en/owners/openhwfoundation) |
| Stars | 1,319 |
| Forks | 560 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2016 |
| Topics | riscv, riscv32imfc |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [openhwfoundation/cv32e40p](https://github.com/openhwfoundation/cv32e40p) |

## Repository

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

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Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.