# openhwfoundation/cv32e40s

<https://repo.masters-masters.com/en/repos/openhwfoundation/cv32e40s>

[Home](https://repo.masters-masters.com/en) › [openhwfoundation](https://repo.masters-masters.com/en/owners/openhwfoundation) › [cv32e40s](https://repo.masters-masters.com/en/repos/openhwfoundation/cv32e40s)

openhwfoundation/cv32e40s has 163 stars on GitHub. Its RepoMasters card: Prototype tier. 4 stage, in-order, secure RISC-V core based on the CV32E40P

| Field | Value |
| --- | --- |
| Owner | [openhwfoundation](https://repo.masters-masters.com/en/owners/openhwfoundation) |
| Stars | 163 |
| Forks | 29 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2021 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [openhwfoundation/cv32e40s](https://github.com/openhwfoundation/cv32e40s) |

## Repository

4 stage, in-order, secure RISC-V core based on the CV32E40P

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by openhwfoundation

- [openhwfoundation/cva6 · ★ 3,185 · Assembly · RC](https://repo.masters-masters.com/en/repos/openhwfoundation/cva6)
- [openhwfoundation/cv32e40p · ★ 1,319 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/openhwfoundation/cv32e40p)
- [openhwfoundation/core-v-verif · ★ 738 · Assembly · Beta](https://repo.masters-masters.com/en/repos/openhwfoundation/core-v-verif)
- [openhwfoundation/cvw · ★ 659 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvw)
- [openhwfoundation/cvfpu · ★ 648 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvfpu)
- [openhwfoundation/core-v-cores · ★ 380 · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/core-v-cores)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.