# openhwfoundation/cva5

<https://repo.masters-masters.com/en/repos/openhwfoundation/cva5>

[Home](https://repo.masters-masters.com/en) › [openhwfoundation](https://repo.masters-masters.com/en/owners/openhwfoundation) › [cva5](https://repo.masters-masters.com/en/repos/openhwfoundation/cva5)

openhwfoundation/cva5 has 140 stars on GitHub. Its RepoMasters card: Prototype tier. The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically…

| Field | Value |
| --- | --- |
| Owner | [openhwfoundation](https://repo.masters-masters.com/en/owners/openhwfoundation) |
| Stars | 140 |
| Forks | 36 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | Apache-2.0 |
| Created | 2022 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [openhwfoundation/cva5](https://github.com/openhwfoundation/cva5) |

## Repository

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by openhwfoundation

- [openhwfoundation/cva6 · ★ 3,185 · Assembly · RC](https://repo.masters-masters.com/en/repos/openhwfoundation/cva6)
- [openhwfoundation/cv32e40p · ★ 1,319 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/openhwfoundation/cv32e40p)
- [openhwfoundation/core-v-verif · ★ 738 · Assembly · Beta](https://repo.masters-masters.com/en/repos/openhwfoundation/core-v-verif)
- [openhwfoundation/cvw · ★ 659 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvw)
- [openhwfoundation/cvfpu · ★ 648 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvfpu)
- [openhwfoundation/core-v-cores · ★ 380 · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/core-v-cores)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.