# openhwfoundation/cvfpu

<https://repo.masters-masters.com/en/repos/openhwfoundation/cvfpu>

[Home](https://repo.masters-masters.com/en) › [openhwfoundation](https://repo.masters-masters.com/en/owners/openhwfoundation) › [cvfpu](https://repo.masters-masters.com/en/repos/openhwfoundation/cvfpu)

openhwfoundation/cvfpu has 648 stars on GitHub. Its RepoMasters card: Alpha tier. Parametric floating-point unit with support for standard RISC-V formats and…

| Field | Value |
| --- | --- |
| Owner | [openhwfoundation](https://repo.masters-masters.com/en/owners/openhwfoundation) |
| Stars | 648 |
| Forks | 175 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | Apache-2.0 |
| Created | 2018 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [openhwfoundation/cvfpu](https://github.com/openhwfoundation/cvfpu) |

## Repository

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by openhwfoundation

- [openhwfoundation/cva6 · ★ 3,185 · Assembly · RC](https://repo.masters-masters.com/en/repos/openhwfoundation/cva6)
- [openhwfoundation/cv32e40p · ★ 1,319 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/openhwfoundation/cv32e40p)
- [openhwfoundation/core-v-verif · ★ 738 · Assembly · Beta](https://repo.masters-masters.com/en/repos/openhwfoundation/core-v-verif)
- [openhwfoundation/cvw · ★ 659 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvw)
- [openhwfoundation/core-v-cores · ★ 380 · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/core-v-cores)
- [openhwfoundation/force-riscv · ★ 321 · C++ · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/force-riscv)

## Nearby in SystemVerilog

- [bespoke-silicon-group/basejump\_stl · ★ 692 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/bespoke-silicon-group/basejump_stl)
- [openhwfoundation/cvw · ★ 659 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvw)
- [raysalemi/uvmprimer · ★ 658 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/raysalemi/uvmprimer)
- [trivialmips/nontrivial-mips · ★ 609 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/trivialmips/nontrivial-mips)
- [lowRISC/lowrisc-chip · ★ 601 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/lowRISC/lowrisc-chip)
- [pulp-platform/pulp · ★ 573 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/pulp)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.