# openhwfoundation/cvw

<https://repo.masters-masters.com/en/repos/openhwfoundation/cvw>

[Home](https://repo.masters-masters.com/en) › [openhwfoundation](https://repo.masters-masters.com/en/owners/openhwfoundation) › [cvw](https://repo.masters-masters.com/en/repos/openhwfoundation/cvw)

openhwfoundation/cvw has 659 stars on GitHub. Its RepoMasters card: Alpha tier. CORE-V Wally is a configurable RISC-V Processor associated with RISC-V…

| Field | Value |
| --- | --- |
| Owner | [openhwfoundation](https://repo.masters-masters.com/en/owners/openhwfoundation) |
| Stars | 659 |
| Forks | 594 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2021 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [openhwfoundation/cvw](https://github.com/openhwfoundation/cvw) |

## Repository

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by openhwfoundation

- [openhwfoundation/cva6 · ★ 3,185 · Assembly · RC](https://repo.masters-masters.com/en/repos/openhwfoundation/cva6)
- [openhwfoundation/cv32e40p · ★ 1,319 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/openhwfoundation/cv32e40p)
- [openhwfoundation/core-v-verif · ★ 738 · Assembly · Beta](https://repo.masters-masters.com/en/repos/openhwfoundation/core-v-verif)
- [openhwfoundation/cvfpu · ★ 648 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvfpu)
- [openhwfoundation/core-v-cores · ★ 380 · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/core-v-cores)
- [openhwfoundation/force-riscv · ★ 321 · C++ · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/force-riscv)

## Nearby in SystemVerilog

- [projf/projf-explore · ★ 799 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/projf/projf-explore)
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- [raysalemi/uvmprimer · ★ 658 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/raysalemi/uvmprimer)
- [openhwfoundation/cvfpu · ★ 648 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/openhwfoundation/cvfpu)
- [trivialmips/nontrivial-mips · ★ 609 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/trivialmips/nontrivial-mips)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.