# openrisc/or1200

<https://repo.masters-masters.com/en/repos/openrisc/or1200>

[Home](https://repo.masters-masters.com/en) › [openrisc](https://repo.masters-masters.com/en/owners/openrisc) › [or1200](https://repo.masters-masters.com/en/repos/openrisc/or1200)

openrisc/or1200 has 184 stars on GitHub. Its RepoMasters card: Prototype tier. OpenRISC 1200 implementation Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [openrisc](https://repo.masters-masters.com/en/owners/openrisc) |
| Stars | 184 |
| Forks | 78 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2014 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [openrisc/or1200](https://github.com/openrisc/or1200) |

## Repository

OpenRISC 1200 implementation

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by openrisc

- [openrisc/mor1kx · ★ 594 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/openrisc/mor1kx)
- [openrisc/orpsoc-cores · ★ 125 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/openrisc/orpsoc-cores)

## Nearby in Verilog

- [thousrm/universal\_NPU-CNN\_accelerator · ★ 185 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/thousrm/universal_NPU-CNN_accelerator)
- [pnnl/OpenCGRA · ★ 184 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/pnnl/OpenCGRA)
- [ash-olakangal/RISC-V-Processor · ★ 184 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ash-olakangal/RISC-V-Processor)
- [zhanghai/archexp · ★ 182 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/zhanghai/archexp)
- [sfmth/OpenSpike · ★ 182 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/sfmth/OpenSpike)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
