# pConst/basic\_verilog

<https://repo.masters-masters.com/en/repos/pConst/basic_verilog>

[Home](https://repo.masters-masters.com/en) › [pConst](https://repo.masters-masters.com/en/owners/pConst) › [basic\_verilog](https://repo.masters-masters.com/en/repos/pConst/basic_verilog)

pConst/basic\_verilog has 2,030 stars on GitHub. Its RepoMasters card: RC tier. Must-have verilog systemverilog modules Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [pConst](https://repo.masters-masters.com/en/owners/pConst) |
| Stars | 2,030 |
| Forks | 423 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2015 |
| Topics | fpga, delay, debounce, encoder, xilinx, altera, verilog, fifo, tcl, spi-master |
| Tier | [RC (2,000 to 4,999 ★)](https://repo.masters-masters.com/en/ranks/blockbuster) |
| View on GitHub | [pConst/basic\_verilog](https://github.com/pConst/basic_verilog) |

## Repository

Must-have verilog systemverilog modules

The tier for repos with 2,000 to 4,999 ★. Published odds per card pulled: 3%. Rarity: Epic.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.