# peilin-chen/Zhulong-RISCV-CPU

<https://repo.masters-masters.com/en/repos/peilin-chen/Zhulong-RISCV-CPU>

[Home](https://repo.masters-masters.com/en) › [peilin-chen](https://repo.masters-masters.com/en/owners/peilin-chen) › [Zhulong-RISCV-CPU](https://repo.masters-masters.com/en/repos/peilin-chen/Zhulong-RISCV-CPU)

peilin-chen/Zhulong-RISCV-CPU has 148 stars on GitHub. Its RepoMasters card: Prototype tier. CPU Design Based on RISCV ISA Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [peilin-chen](https://repo.masters-masters.com/en/owners/peilin-chen) |
| Stars | 148 |
| Forks | 25 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2024 |
| Topics | integrated-circuits, processor-design |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [peilin-chen/Zhulong-RISCV-CPU](https://github.com/peilin-chen/Zhulong-RISCV-CPU) |

## Repository

CPU Design Based on RISCV ISA

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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- [neelkshah/MIPS-Processor · ★ 146 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/neelkshah/MIPS-Processor)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.