# phoeniX-Digital-Design/phoeniX

<https://repo.masters-masters.com/en/repos/phoeniX-Digital-Design/phoeniX>

[Home](https://repo.masters-masters.com/en) › [phoeniX-Digital-Design](https://repo.masters-masters.com/en/owners/phoeniX-Digital-Design) › [phoeniX](https://repo.masters-masters.com/en/repos/phoeniX-Digital-Design/phoeniX)

phoeniX-Digital-Design/phoeniX has 132 stars on GitHub. Its RepoMasters card: Prototype tier. A Reconfigurable RISC-V Core for Approximate Computing

| Field | Value |
| --- | --- |
| Owner | [phoeniX-Digital-Design](https://repo.masters-masters.com/en/owners/phoeniX-Digital-Design) |
| Stars | 132 |
| Forks | 83 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2023 |
| Topics | cpu-design, computer-architecture, fpga, vlsi, microprocessor, riscv, risc-v, cpu, embedded-systems, approximate-computing |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [phoeniX-Digital-Design/phoeniX](https://github.com/phoeniX-Digital-Design/phoeniX) |

## Repository

A Reconfigurable RISC-V Core for Approximate Computing

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [MiSTer-devel/Genesis\_MiSTer · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MiSTer-devel/Genesis_MiSTer)
- [circuitgraph/circuitgraph · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/circuitgraph/circuitgraph)
- [mole99/gf180mcu-fabulous-fpga · ★ 132 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/mole99/gf180mcu-fabulous-fpga)
- [jotego/jt12 · ★ 131 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/jotego/jt12)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.