# pulp-platform/axi

<https://repo.masters-masters.com/en/repos/pulp-platform/axi>

[Home](https://repo.masters-masters.com/en) › [pulp-platform](https://repo.masters-masters.com/en/owners/pulp-platform) › [axi](https://repo.masters-masters.com/en/repos/pulp-platform/axi)

pulp-platform/axi has 1,745 stars on GitHub. Its RepoMasters card: Beta tier. AXI SystemVerilog synthesizable IP modules and verification infrastructure for…

| Field | Value |
| --- | --- |
| Owner | [pulp-platform](https://repo.masters-masters.com/en/owners/pulp-platform) |
| Stars | 1,745 |
| Forks | 378 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2018 |
| Topics | axi, axi4, axi4-lite, systemverilog, hardware, network-on-chip, asic, fpga, rtl, ip |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [pulp-platform/axi](https://github.com/pulp-platform/axi) |

## Repository

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## More repos by pulp-platform

- [pulp-platform/pulpino · ★ 1,074 · C · Beta](https://repo.masters-masters.com/en/repos/pulp-platform/pulpino)
- [pulp-platform/common\_cells · ★ 814 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/pulp-platform/common_cells)
- [pulp-platform/pulp-dronet · ★ 630 · C · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/pulp-dronet)
- [pulp-platform/pulp · ★ 573 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/pulp)
- [pulp-platform/ara · ★ 562 · C · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/ara)
- [pulp-platform/pulpissimo · ★ 504 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/pulp-platform/pulpissimo)

## Nearby in SystemVerilog

- [verilator/verilator · ★ 4,052 · SystemVerilog · RC](https://repo.masters-masters.com/en/repos/verilator/verilator)
- [lowRISC/opentitan · ★ 3,728 · SystemVerilog · RC](https://repo.masters-masters.com/en/repos/lowRISC/opentitan)
- [lowRISC/ibex · ★ 2,150 · SystemVerilog · RC](https://repo.masters-masters.com/en/repos/lowRISC/ibex)
- [aws/aws-fpga · ★ 1,691 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/aws/aws-fpga)
- [itsfrank/MinecraftHDL · ★ 1,596 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/itsfrank/MinecraftHDL)
- [hughperkins/VeriGPU · ★ 1,402 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/hughperkins/VeriGPU)

---
Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.