# racerxdl/riskow

<https://repo.masters-masters.com/en/repos/racerxdl/riskow>

[Home](https://repo.masters-masters.com/en) › [racerxdl](https://repo.masters-masters.com/en/owners/racerxdl) › [riskow](https://repo.masters-masters.com/en/repos/racerxdl/riskow)

racerxdl/riskow has 144 stars on GitHub. Its RepoMasters card: Prototype tier. Learning how to make a RISC-V Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [racerxdl](https://repo.masters-masters.com/en/owners/racerxdl) |
| Stars | 144 |
| Forks | 12 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2020 |
| Topics | fpga, learning-exercise, open-core, opencore, risc-v, verilog, riskow |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [racerxdl/riskow](https://github.com/racerxdl/riskow) |

## Repository

Learning how to make a RISC-V

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by racerxdl

- [racerxdl/stm32f0-pico-dump · ★ 198 · C · Prototype](https://repo.masters-masters.com/en/repos/racerxdl/stm32f0-pico-dump)

## Nearby in Verilog

- [aquaxis/IPCORE · ★ 144 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/aquaxis/IPCORE)
- [mattvenn/basic-ecp5-pcb · ★ 144 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/mattvenn/basic-ecp5-pcb)
- [MoonshotAI/nano-kpu · ★ 144 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/MoonshotAI/nano-kpu)
- [abdelazeem201/Cadence-RTL-to-GDSII-Flow · ★ 141 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/abdelazeem201/Cadence-RTL-to-GDSII-Flow)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.