# rafaelcalcada/rvx

<https://repo.masters-masters.com/en/repos/rafaelcalcada/rvx>

[Home](https://repo.masters-masters.com/en) › [rafaelcalcada](https://repo.masters-masters.com/en/owners/rafaelcalcada) › [rvx](https://repo.masters-masters.com/en/repos/rafaelcalcada/rvx)

rafaelcalcada/rvx has 203 stars on GitHub. Its RepoMasters card: Prototype tier. RISC-V microcontroller IP for embedded, FPGA and ASIC applications

| Field | Value |
| --- | --- |
| Owner | [rafaelcalcada](https://repo.masters-masters.com/en/owners/rafaelcalcada) |
| Stars | 203 |
| Forks | 29 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2020 |
| Topics | risc-v, rv32i, core, riscv, uart, zicsr, cpu, gpio, mcu, microcontroller |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [rafaelcalcada/rvx](https://github.com/rafaelcalcada/rvx) |

## Repository

RISC-V microcontroller IP for embedded, FPGA and ASIC applications

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [Lichee-Pi/Tang\_E203\_Mini · ★ 204 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/Lichee-Pi/Tang_E203_Mini)
- [jamieiles/uart · ★ 203 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/jamieiles/uart)
- [AngeloJacobo/FPGA\_Book\_Experiments · ★ 203 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/AngeloJacobo/FPGA_Book_Experiments)
- [taoyilee/clacc · ★ 202 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/taoyilee/clacc)
- [pwmarcz/fpga-chip8 · ★ 202 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/pwmarcz/fpga-chip8)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.