# regymm/quasiSoC

<https://repo.masters-masters.com/en/repos/regymm/quasiSoC>

[Home](https://repo.masters-masters.com/en) › [regymm](https://repo.masters-masters.com/en/owners/regymm) › [quasiSoC](https://repo.masters-masters.com/en/repos/regymm/quasiSoC)

regymm/quasiSoC has 166 stars on GitHub. Its RepoMasters card: Prototype tier. Linux capable RISC-V SoC designed to be readable and useful. Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [regymm](https://repo.masters-masters.com/en/owners/regymm) |
| Stars | 166 |
| Forks | 11 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2021 |
| Topics | fpga, risc-v |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [regymm/quasiSoC](https://github.com/regymm/quasiSoC) |

## Repository

Linux capable RISC-V SoC designed to be readable and useful.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by regymm

- [regymm/PYNQSDR · ★ 129 · Prototype](https://repo.masters-masters.com/en/repos/regymm/PYNQSDR)

## Nearby in Verilog

- [chriz2600/DreamcastHDMI · ★ 167 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/chriz2600/DreamcastHDMI)
- [lisper/cpus-caddr · ★ 166 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/lisper/cpus-caddr)
- [onchipuis/mriscv · ★ 166 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/onchipuis/mriscv)
- [drandyhaas/Haasoscope · ★ 165 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/drandyhaas/Haasoscope)
- [mhyousefi/MIPS-pipeline-processor · ★ 164 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/mhyousefi/MIPS-pipeline-processor)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.