# rj45/rj32

<https://repo.masters-masters.com/en/repos/rj45/rj32>

[Home](https://repo.masters-masters.com/en) › [rj45](https://repo.masters-masters.com/en/owners/rj45) › [rj32](https://repo.masters-masters.com/en/repos/rj45/rj32)

rj45/rj32 has 136 stars on GitHub. Its RepoMasters card: Prototype tier. A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

| Field | Value |
| --- | --- |
| Owner | [rj45](https://repo.masters-masters.com/en/owners/rj45) |
| Stars | 136 |
| Forks | 20 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | MIT |
| Created | 2021 |
| Topics | cpu, verilog, fpga, vga, dvi, simulator, simulation, processor |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [rj45/rj32](https://github.com/rj45/rj32) |

## Repository

A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.