# russdill/bch\_verilog

<https://repo.masters-masters.com/en/repos/russdill/bch_verilog>

[Home](https://repo.masters-masters.com/en) › [russdill](https://repo.masters-masters.com/en/owners/russdill) › [bch\_verilog](https://repo.masters-masters.com/en/repos/russdill/bch_verilog)

russdill/bch\_verilog has 139 stars on GitHub. Its RepoMasters card: Prototype tier. Verilog based BCH encoder/decoder Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [russdill](https://repo.masters-masters.com/en/owners/russdill) |
| Stars | 139 |
| Forks | 48 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2014 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [russdill/bch\_verilog](https://github.com/russdill/bch_verilog) |

## Repository

Verilog based BCH encoder/decoder

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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- [russdill/juniper-vpn-py · ★ 113 · Python · Prototype](https://repo.masters-masters.com/en/repos/russdill/juniper-vpn-py)

## Nearby in Verilog

- [HDLForBeginners/Examples · ★ 140 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/HDLForBeginners/Examples)
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- [open-fpga/core-template · ★ 139 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/open-fpga/core-template)
- [efabless/caravel\_mpw-one · ★ 138 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/efabless/caravel_mpw-one)
- [NXP/i3c-slave-design · ★ 137 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/NXP/i3c-slave-design)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.