# snbk001/Verilog-Design-Examples

<https://repo.masters-masters.com/en/repos/snbk001/Verilog-Design-Examples>

[Home](https://repo.masters-masters.com/en) › [snbk001](https://repo.masters-masters.com/en/owners/snbk001) › [Verilog-Design-Examples](https://repo.masters-masters.com/en/repos/snbk001/Verilog-Design-Examples)

snbk001/Verilog-Design-Examples has 234 stars on GitHub. Its RepoMasters card: Prototype tier. Verilog Design Examples with self checking testbenches. Half…

| Field | Value |
| --- | --- |
| Owner | [snbk001](https://repo.masters-masters.com/en/owners/snbk001) |
| Stars | 234 |
| Forks | 40 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2022 |
| Topics | verilog, testbenches, verilog-design, verilog-code, verilog-hdl, verilog-programs, verilog-project, self-checking |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [snbk001/Verilog-Design-Examples](https://github.com/snbk001/Verilog-Design-Examples) |

## Repository

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM,…

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.