# stevehoover/warp-v

<https://repo.masters-masters.com/en/repos/stevehoover/warp-v>

[Home](https://repo.masters-masters.com/en) › [stevehoover](https://repo.masters-masters.com/en/owners/stevehoover) › [warp-v](https://repo.masters-masters.com/en/repos/stevehoover/warp-v)

stevehoover/warp-v has 257 stars on GitHub. Its RepoMasters card: Alpha tier. WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

| Field | Value |
| --- | --- |
| Owner | [stevehoover](https://repo.masters-masters.com/en/owners/stevehoover) |
| Stars | 257 |
| Forks | 60 |
| Language | [TL-Verilog](https://repo.masters-masters.com/en/languages/tl-verilog) |
| License | BSD-3-Clause |
| Created | 2018 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [stevehoover/warp-v](https://github.com/stevehoover/warp-v) |

## Repository

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

## More repos by stevehoover

- [stevehoover/LF-Building-a-RISC-V-CPU-Core · ★ 519 · TL-Verilog · Alpha](https://repo.masters-masters.com/en/repos/stevehoover/LF-Building-a-RISC-V-CPU-Core)
- [stevehoover/RISC-V\_MYTH\_Workshop · ★ 105 · TL-Verilog · Prototype](https://repo.masters-masters.com/en/repos/stevehoover/RISC-V_MYTH_Workshop)

## Nearby in TL-Verilog

- [stevehoover/LF-Building-a-RISC-V-CPU-Core · ★ 519 · TL-Verilog · Alpha](https://repo.masters-masters.com/en/repos/stevehoover/LF-Building-a-RISC-V-CPU-Core)
- [os-fpga/Virtual-FPGA-Lab · ★ 284 · TL-Verilog · Alpha](https://repo.masters-masters.com/en/repos/os-fpga/Virtual-FPGA-Lab)
- [stevehoover/RISC-V\_MYTH\_Workshop · ★ 105 · TL-Verilog · Prototype](https://repo.masters-masters.com/en/repos/stevehoover/RISC-V_MYTH_Workshop)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.