# stnolting/neorv32-setups

<https://repo.masters-masters.com/en/repos/stnolting/neorv32-setups>

[Home](https://repo.masters-masters.com/en) › [stnolting](https://repo.masters-masters.com/en/owners/stnolting) › [neorv32-setups](https://repo.masters-masters.com/en/repos/stnolting/neorv32-setups)

stnolting/neorv32-setups has 102 stars on GitHub. Its RepoMasters card: Prototype tier. 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and…

| Field | Value |
| --- | --- |
| Owner | [stnolting](https://repo.masters-masters.com/en/owners/stnolting) |
| Stars | 102 |
| Forks | 41 |
| Language | [VHDL](https://repo.masters-masters.com/en/languages/vhdl) |
| License | BSD-3-Clause |
| Created | 2022 |
| Topics | neorv32, fpga, xilinx, intel, lattice, ghdl, yosys, soc, risc-v, vhdl |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [stnolting/neorv32-setups](https://github.com/stnolting/neorv32-setups) |

## Repository

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by stnolting

- [stnolting/neorv32 · ★ 2,302 · VHDL · RC](https://repo.masters-masters.com/en/repos/stnolting/neorv32)
- [stnolting/neoTRNG · ★ 231 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/stnolting/neoTRNG)
- [stnolting/neo430 · ★ 212 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/stnolting/neo430)
- [stnolting/fpga\_puf · ★ 145 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/stnolting/fpga_puf)
- [stnolting/riscv-gcc-prebuilt · ★ 107 · Shell · Prototype](https://repo.masters-masters.com/en/repos/stnolting/riscv-gcc-prebuilt)
- [stnolting/captouch · ★ 106 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/stnolting/captouch)

## Nearby in VHDL

- [OldGlycine/BJUT-CS · ★ 104 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/OldGlycine/BJUT-CS)
- [inmcm/Simon\_Speck\_Ciphers · ★ 103 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/inmcm/Simon_Speck_Ciphers)
- [mincer-ray/openfpga-GBA · ★ 103 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/mincer-ray/openfpga-GBA)
- [stnolting/neorv32-verilog · ★ 101 · VHDL · Prototype](https://repo.masters-masters.com/en/repos/stnolting/neorv32-verilog)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.