# stnolting/neorv32-verilog

<https://repo.masters-masters.com/en/repos/stnolting/neorv32-verilog>

[Home](https://repo.masters-masters.com/en) › [stnolting](https://repo.masters-masters.com/en/owners/stnolting) › [neorv32-verilog](https://repo.masters-masters.com/en/repos/stnolting/neorv32-verilog)

stnolting/neorv32-verilog has 101 stars on GitHub. Its RepoMasters card: Prototype tier. ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog…

| Field | Value |
| --- | --- |
| Owner | [stnolting](https://repo.masters-masters.com/en/owners/stnolting) |
| Stars | 101 |
| Forks | 15 |
| Language | [VHDL](https://repo.masters-masters.com/en/languages/vhdl) |
| License | BSD-3-Clause |
| Created | 2022 |
| Topics | asic, fpga, ghdl, neorv32, verilog, icarus-verilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [stnolting/neorv32-verilog](https://github.com/stnolting/neorv32-verilog) |

## Repository

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Archived: this repository is read-only

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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