# subbdue/systemverilog.io

<https://repo.masters-masters.com/en/repos/subbdue/systemverilog.io>

[Home](https://repo.masters-masters.com/en) › [subbdue](https://repo.masters-masters.com/en/owners/subbdue) › [systemverilog.io](https://repo.masters-masters.com/en/repos/subbdue/systemverilog.io)

subbdue/systemverilog.io has 226 stars on GitHub. Its RepoMasters card: Prototype tier. Code used in Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [subbdue](https://repo.masters-masters.com/en/owners/subbdue) |
| Stars | 226 |
| Forks | 32 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2016 |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [subbdue/systemverilog.io](https://github.com/subbdue/systemverilog.io) |

## Repository

Code used in

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in SystemVerilog

- [zama-ai/hpu\_fpga · ★ 233 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/zama-ai/hpu_fpga)
- [pulp-platform/snitch · ★ 229 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/pulp-platform/snitch)
- [svunit/svunit · ★ 227 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/svunit/svunit)
- [agg23/openfpga-NES · ★ 224 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/agg23/openfpga-NES)
- [taichi-ishitani/tnoc · ★ 216 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/taichi-ishitani/tnoc)
- [tilk/riscv-simple-sv · ★ 216 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/tilk/riscv-simple-sv)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.
