# syntacore/scr1

<https://repo.masters-masters.com/en/repos/syntacore/scr1>

[Home](https://repo.masters-masters.com/en) › [syntacore](https://repo.masters-masters.com/en/owners/syntacore) › [scr1](https://repo.masters-masters.com/en/repos/syntacore/scr1)

syntacore/scr1 has 1,013 stars on GitHub. Its RepoMasters card: Beta tier. SCR1 is a high-quality open-source RISC-V MCU core in Verilog

| Field | Value |
| --- | --- |
| Owner | [syntacore](https://repo.masters-masters.com/en/owners/syntacore) |
| Stars | 1,013 |
| Forks | 367 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2017 |
| Topics | riscv, risc-v, rtl, verilog, rv32i, rv32e, rv32imc, rv32emc, ip, core |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [syntacore/scr1](https://github.com/syntacore/scr1) |

## Repository

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## Nearby in SystemVerilog

- [openhwfoundation/cv32e40p · ★ 1,319 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/openhwfoundation/cv32e40p)
- [hdl-util/hdmi · ★ 1,310 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/hdl-util/hdmi)
- [rsd-devel/rsd · ★ 1,214 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/rsd-devel/rsd)
- [fpganinja/taxi · ★ 1,004 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/fpganinja/taxi)
- [chipsalliance/Cores-VeeR-EH1 · ★ 971 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/chipsalliance/Cores-VeeR-EH1)
- [westerndigitalcorporation/swerv\_eh1 · ★ 882 · SystemVerilog · Beta](https://repo.masters-masters.com/en/repos/westerndigitalcorporation/swerv_eh1)

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Data: GitHub · Illustration: the project’s public image, pixelated by RepoMasters.