# thedatabusdotio/fpga-ml-accelerator

<https://repo.masters-masters.com/en/repos/thedatabusdotio/fpga-ml-accelerator>

[Home](https://repo.masters-masters.com/en) › [thedatabusdotio](https://repo.masters-masters.com/en/owners/thedatabusdotio) › [fpga-ml-accelerator](https://repo.masters-masters.com/en/repos/thedatabusdotio/fpga-ml-accelerator)

thedatabusdotio/fpga-ml-accelerator has 198 stars on GitHub. Its RepoMasters card: Prototype tier. This repository hosts the code for an FPGA based…

| Field | Value |
| --- | --- |
| Owner | [thedatabusdotio](https://repo.masters-masters.com/en/owners/thedatabusdotio) |
| Stars | 198 |
| Forks | 36 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2020 |
| Topics | fpga, hardware, digital-design, verilog-hdl, vhdl, asic, verification |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [thedatabusdotio/fpga-ml-accelerator](https://github.com/thedatabusdotio/fpga-ml-accelerator) |

## Repository

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## Nearby in Verilog

- [sumanth-kalluri/cnn\_hardware\_acclerator\_for\_fpga · ★ 199 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/sumanth-kalluri/cnn_hardware_acclerator_for_fpga)
- [benreynwar/fft-dit-fpga · ★ 198 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/benreynwar/fft-dit-fpga)
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- [hrvach/fpg1 · ★ 195 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/hrvach/fpg1)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.