# trivialmips/TrivialMIPS

<https://repo.masters-masters.com/en/repos/trivialmips/TrivialMIPS>

[Home](https://repo.masters-masters.com/en) › [trivialmips](https://repo.masters-masters.com/en/owners/trivialmips) › [TrivialMIPS](https://repo.masters-masters.com/en/repos/trivialmips/TrivialMIPS)

trivialmips/TrivialMIPS has 110 stars on GitHub. Its RepoMasters card: Prototype tier. MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

| Field | Value |
| --- | --- |
| Owner | [trivialmips](https://repo.masters-masters.com/en/owners/trivialmips) |
| Stars | 110 |
| Forks | 35 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | None |
| Created | 2018 |
| Topics | systemverilog, mips, fpga, xilinx, cpu, fpga-soc |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [trivialmips/TrivialMIPS](https://github.com/trivialmips/TrivialMIPS) |

## Repository

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by trivialmips

- [trivialmips/nontrivial-mips · ★ 609 · SystemVerilog · Alpha](https://repo.masters-masters.com/en/repos/trivialmips/nontrivial-mips)

## Nearby in SystemVerilog

- [Verdvana/AXI4\_Interconnect · ★ 111 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/Verdvana/AXI4_Interconnect)
- [ttchisholm/10g-low-latency-ethernet · ★ 111 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/ttchisholm/10g-low-latency-ethernet)
- [RoaLogic/ahb3lite\_interconnect · ★ 110 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/RoaLogic/ahb3lite_interconnect)
- [eliaskousk/parallella-riscv · ★ 109 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/eliaskousk/parallella-riscv)
- [mmxsrup/axi4-interface · ★ 109 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/mmxsrup/axi4-interface)
- [Weiyet/MakerCode\_RTLChallenge · ★ 109 · SystemVerilog · Prototype](https://repo.masters-masters.com/en/repos/Weiyet/MakerCode_RTLChallenge)

---
Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.