# tscheipel/HaDes-V

<https://repo.masters-masters.com/en/repos/tscheipel/HaDes-V>

[Home](https://repo.masters-masters.com/en) › [tscheipel](https://repo.masters-masters.com/en/owners/tscheipel) › [HaDes-V](https://repo.masters-masters.com/en/repos/tscheipel/HaDes-V)

tscheipel/HaDes-V has 198 stars on GitHub. Its RepoMasters card: Prototype tier. HaDes-V is an Open Educational Resource for learning microcontroller design…

| Field | Value |
| --- | --- |
| Owner | [tscheipel](https://repo.masters-masters.com/en/owners/tscheipel) |
| Stars | 198 |
| Forks | 106 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | MIT |
| Created | 2024 |
| Topics | assembly-programming, c-programming, computer-architecture, gtkwave, hardware-software-codesign, microcontroller-design, open-educational-resources, pipelines, processor-architecture, processor-design |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [tscheipel/HaDes-V](https://github.com/tscheipel/HaDes-V) |

## Repository

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practic…

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.