# ttchisholm/10g-low-latency-ethernet

<https://repo.masters-masters.com/en/repos/ttchisholm/10g-low-latency-ethernet>

[Home](https://repo.masters-masters.com/en) › [ttchisholm](https://repo.masters-masters.com/en/owners/ttchisholm) › [10g-low-latency-ethernet](https://repo.masters-masters.com/en/repos/ttchisholm/10g-low-latency-ethernet)

ttchisholm/10g-low-latency-ethernet has 111 stars on GitHub. Its RepoMasters card: Prototype tier. 10G Low Latency Ethernet Language: SystemVerilog.

| Field | Value |
| --- | --- |
| Owner | [ttchisholm](https://repo.masters-masters.com/en/owners/ttchisholm) |
| Stars | 111 |
| Forks | 34 |
| Language | [SystemVerilog](https://repo.masters-masters.com/en/languages/systemverilog) |
| License | MIT |
| Created | 2022 |
| Topics | cocotb, ethernet, fpga, pyuvm, systemverilog, xilinx |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ttchisholm/10g-low-latency-ethernet](https://github.com/ttchisholm/10g-low-latency-ethernet) |

## Repository

10G Low Latency Ethernet

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.