# ultraembedded/biriscv

<https://repo.masters-masters.com/en/repos/ultraembedded/biriscv>

[Home](https://repo.masters-masters.com/en) › [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) › [biriscv](https://repo.masters-masters.com/en/repos/ultraembedded/biriscv)

ultraembedded/biriscv has 1,329 stars on GitHub. Its RepoMasters card: Beta tier. 32-bit Superscalar RISC-V CPU Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) |
| Stars | 1,329 |
| Forks | 205 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2020 |
| Topics | risc-v, rv32i, rv32im, superscalar, cpu, fpga, verilog, pipelined-processors, verilator, coremark |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [ultraembedded/biriscv](https://github.com/ultraembedded/biriscv) |

## Repository

32-bit Superscalar RISC-V CPU

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## More repos by ultraembedded

- [ultraembedded/riscv · ★ 1,812 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/riscv)
- [ultraembedded/cores · ★ 940 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/cores)
- [ultraembedded/core\_ddr3\_controller · ★ 646 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_ddr3_controller)
- [ultraembedded/FPGAmp · ★ 307 · C · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/FPGAmp)
- [ultraembedded/core\_jpeg · ★ 283 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_jpeg)
- [ultraembedded/riscv\_soc · ★ 213 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/riscv_soc)

## Nearby in Verilog

- [aolofsson/oh · ★ 1,439 · Verilog · Beta](https://repo.masters-masters.com/en/repos/aolofsson/oh)
- [VerticalResearchGroup/miaow · ★ 1,432 · Verilog · Beta](https://repo.masters-masters.com/en/repos/VerticalResearchGroup/miaow)
- [tiny-tpu-v2/tiny-tpu · ★ 1,412 · Verilog · Beta](https://repo.masters-masters.com/en/repos/tiny-tpu-v2/tiny-tpu)
- [EttusResearch/uhd · ★ 1,296 · Verilog · Beta](https://repo.masters-masters.com/en/repos/EttusResearch/uhd)
- [Digital-EDA/Digital-IDE · ★ 1,191 · Verilog · Beta](https://repo.masters-masters.com/en/repos/Digital-EDA/Digital-IDE)
- [circuitvalley/USB\_C\_Industrial\_Camera\_FPGA\_USB3 · ★ 1,170 · Verilog · Beta](https://repo.masters-masters.com/en/repos/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.