# ultraembedded/core\_audio

<https://repo.masters-masters.com/en/repos/ultraembedded/core_audio>

[Home](https://repo.masters-masters.com/en) › [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) › [core\_audio](https://repo.masters-masters.com/en/repos/ultraembedded/core_audio)

ultraembedded/core\_audio has 101 stars on GitHub. Its RepoMasters card: Prototype tier. Audio controller (I2S, SPDIF, DAC) Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) |
| Stars | 101 |
| Forks | 19 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-2.0 |
| Created | 2019 |
| Topics | i2s, spdif, dac, audio, axi4-lite, verilog, fpga |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ultraembedded/core\_audio](https://github.com/ultraembedded/core_audio) |

## Repository

Audio controller (I2S, SPDIF, DAC)

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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- [dawsonjon/verilog-math · ★ 101 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/dawsonjon/verilog-math)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.