# ultraembedded/core\_ddr3\_controller

<https://repo.masters-masters.com/en/repos/ultraembedded/core_ddr3_controller>

[Home](https://repo.masters-masters.com/en) › [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) › [core\_ddr3\_controller](https://repo.masters-masters.com/en/repos/ultraembedded/core_ddr3_controller)

ultraembedded/core\_ddr3\_controller has 644 stars on GitHub. Its RepoMasters card: Alpha tier. A DDR3 memory controller in Verilog for various FPGAs

| Field | Value |
| --- | --- |
| Owner | [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) |
| Stars | 644 |
| Forks | 111 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2020 |
| Tier | [Alpha (250 to 699 ★)](https://repo.masters-masters.com/en/ranks/b_movie) |
| View on GitHub | [ultraembedded/core\_ddr3\_controller](https://github.com/ultraembedded/core_ddr3_controller) |

## Repository

A DDR3 memory controller in Verilog for various FPGAs

The tier for repos with 250 to 699 ★. Published odds per card pulled: 20%. Rarity: Uncommon.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.