# ultraembedded/core\_sdram\_axi4

<https://repo.masters-masters.com/en/repos/ultraembedded/core_sdram_axi4>

[Home](https://repo.masters-masters.com/en) › [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) › [core\_sdram\_axi4](https://repo.masters-masters.com/en/repos/ultraembedded/core_sdram_axi4)

ultraembedded/core\_sdram\_axi4 has 110 stars on GitHub. Its RepoMasters card: Prototype tier. SDRAM controller with AXI4 interface Language: C++.

| Field | Value |
| --- | --- |
| Owner | [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) |
| Stars | 110 |
| Forks | 32 |
| Language | [C++](https://repo.masters-masters.com/en/languages/c-plus-plus) |
| License | GPL-3.0 |
| Created | 2019 |
| Topics | verilog, axi4, sdram-controller, fpga |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ultraembedded/core\_sdram\_axi4](https://github.com/ultraembedded/core_sdram_axi4) |

## Repository

SDRAM controller with AXI4 interface

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.