# ultraembedded/cores

<https://repo.masters-masters.com/en/repos/ultraembedded/cores>

[Home](https://repo.masters-masters.com/en) › [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) › [cores](https://repo.masters-masters.com/en/repos/ultraembedded/cores)

ultraembedded/cores has 940 stars on GitHub. Its RepoMasters card: Beta tier. Various HDL (Verilog) IP Cores Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) |
| Stars | 940 |
| Forks | 238 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2015 |
| Topics | verilog, rtl, verilog-hdl, fpga, verilator, verilog-components, asic, sdram, sram, audio |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [ultraembedded/cores](https://github.com/ultraembedded/cores) |

## Repository

Various HDL (Verilog) IP Cores

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## More repos by ultraembedded

- [ultraembedded/riscv · ★ 1,812 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/riscv)
- [ultraembedded/biriscv · ★ 1,329 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/biriscv)
- [ultraembedded/core\_ddr3\_controller · ★ 646 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_ddr3_controller)
- [ultraembedded/FPGAmp · ★ 307 · C · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/FPGAmp)
- [ultraembedded/core\_jpeg · ★ 283 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_jpeg)
- [ultraembedded/riscv\_soc · ★ 213 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/riscv_soc)

## Nearby in Verilog

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- [WangXuan95/FPGA-FOC · ★ 994 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-FOC)
- [WangXuan95/FPGA-USB-Device · ★ 934 · Verilog · Beta](https://repo.masters-masters.com/en/repos/WangXuan95/FPGA-USB-Device)
- [open-sdr/openwifi-hw · ★ 917 · Verilog · Beta](https://repo.masters-masters.com/en/repos/open-sdr/openwifi-hw)
- [FeSens/openTPU · ★ 907 · Verilog · Beta](https://repo.masters-masters.com/en/repos/FeSens/openTPU)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.