# ultraembedded/openlogicbit

<https://repo.masters-masters.com/en/repos/ultraembedded/openlogicbit>

[Home](https://repo.masters-masters.com/en) › [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) › [openlogicbit](https://repo.masters-masters.com/en/repos/ultraembedded/openlogicbit)

ultraembedded/openlogicbit has 178 stars on GitHub. Its RepoMasters card: Prototype tier. Open-source Logic Analyzer gateware for various FPGA dev…

| Field | Value |
| --- | --- |
| Owner | [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) |
| Stars | 178 |
| Forks | 24 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | Apache-2.0 |
| Created | 2021 |
| Topics | fpga, logic-analyzer, xilinx-fpga, lattice-fpga, altera-fpga, ftdi232h, ftdi2232h, digital-signal-analyzer, verilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ultraembedded/openlogicbit](https://github.com/ultraembedded/openlogicbit) |

## Repository

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.