# ultraembedded/riscv

<https://repo.masters-masters.com/en/repos/ultraembedded/riscv>

[Home](https://repo.masters-masters.com/en) › [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) › [riscv](https://repo.masters-masters.com/en/repos/ultraembedded/riscv)

ultraembedded/riscv has 1,812 stars on GitHub. Its RepoMasters card: Beta tier. RISC-V CPU Core (RV32IM) Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) |
| Stars | 1,812 |
| Forks | 294 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | BSD-3-Clause |
| Created | 2014 |
| Topics | risc-v, cpu, verilog, fpga, verilator, rv32im, rv32i, riscv-linux, pipeline-processor, asic |
| Tier | [Beta (700 to 1,999 ★)](https://repo.masters-masters.com/en/ranks/box_office) |
| View on GitHub | [ultraembedded/riscv](https://github.com/ultraembedded/riscv) |

## Repository

RISC-V CPU Core (RV32IM)

The tier for repos with 700 to 1,999 ★. Published odds per card pulled: 6%. Rarity: Rare.

## More repos by ultraembedded

- [ultraembedded/biriscv · ★ 1,329 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/biriscv)
- [ultraembedded/cores · ★ 940 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/cores)
- [ultraembedded/core\_ddr3\_controller · ★ 646 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_ddr3_controller)
- [ultraembedded/FPGAmp · ★ 307 · C · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/FPGAmp)
- [ultraembedded/core\_jpeg · ★ 283 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_jpeg)
- [ultraembedded/riscv\_soc · ★ 213 · Verilog · Prototype](https://repo.masters-masters.com/en/repos/ultraembedded/riscv_soc)

## Nearby in Verilog

- [riscv-mcu/e203\_hbirdv2 · ★ 1,973 · Verilog · Beta](https://repo.masters-masters.com/en/repos/riscv-mcu/e203_hbirdv2)
- [olofk/serv · ★ 1,915 · Verilog · Beta](https://repo.masters-masters.com/en/repos/olofk/serv)
- [ufrisk/pcileech-fpga · ★ 1,852 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ufrisk/pcileech-fpga)
- [alexforencich/verilog-pcie · ★ 1,675 · Verilog · Beta](https://repo.masters-masters.com/en/repos/alexforencich/verilog-pcie)
- [ZipCPU/zipcpu · ★ 1,597 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ZipCPU/zipcpu)
- [XUANTIE-RV/openc910 · ★ 1,492 · Verilog · Beta](https://repo.masters-masters.com/en/repos/XUANTIE-RV/openc910)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.