# ultraembedded/riscv\_soc

<https://repo.masters-masters.com/en/repos/ultraembedded/riscv_soc>

[Home](https://repo.masters-masters.com/en) › [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) › [riscv\_soc](https://repo.masters-masters.com/en/repos/ultraembedded/riscv_soc)

ultraembedded/riscv\_soc has 213 stars on GitHub. Its RepoMasters card: Prototype tier. Basic RISC-V Test SoC Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [ultraembedded](https://repo.masters-masters.com/en/owners/ultraembedded) |
| Stars | 213 |
| Forks | 40 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2019 |
| Topics | risc-v, system-on-chip, verilog, systemc, fpga-soc, fpga-soc-linux, linux, riscv-linux |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [ultraembedded/riscv\_soc](https://github.com/ultraembedded/riscv_soc) |

## Repository

Basic RISC-V Test SoC

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

## More repos by ultraembedded

- [ultraembedded/riscv · ★ 1,812 · Verilog · Beta](https://repo.masters-masters.com/en/repos/ultraembedded/riscv)
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- [ultraembedded/core\_jpeg · ★ 283 · Verilog · Alpha](https://repo.masters-masters.com/en/repos/ultraembedded/core_jpeg)

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.