# z4yx/NaiveMIPS-HDL

<https://repo.masters-masters.com/en/repos/z4yx/NaiveMIPS-HDL>

[Home](https://repo.masters-masters.com/en) › [z4yx](https://repo.masters-masters.com/en/owners/z4yx) › [NaiveMIPS-HDL](https://repo.masters-masters.com/en/repos/z4yx/NaiveMIPS-HDL)

z4yx/NaiveMIPS-HDL has 117 stars on GitHub. Its RepoMasters card: Prototype tier. Naïve MIPS32 SoC implementation Language: Verilog.

| Field | Value |
| --- | --- |
| Owner | [z4yx](https://repo.masters-masters.com/en/owners/z4yx) |
| Stars | 117 |
| Forks | 35 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | None |
| Created | 2017 |
| Topics | mips, cpu, verilog |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [z4yx/NaiveMIPS-HDL](https://github.com/z4yx/NaiveMIPS-HDL) |

## Repository

Naïve MIPS32 SoC implementation

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.