# zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

<https://repo.masters-masters.com/en/repos/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial>

[Home](https://repo.masters-masters.com/en) › [zslwyuan](https://repo.masters-masters.com/en/owners/zslwyuan) › [Basic-SIMD-Processor-Verilog-Tutorial](https://repo.masters-masters.com/en/repos/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial)

zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial has 160 stars on GitHub. Its RepoMasters card: Prototype tier. Implementation of a simple SIMD processor in…

| Field | Value |
| --- | --- |
| Owner | [zslwyuan](https://repo.masters-masters.com/en/owners/zslwyuan) |
| Stars | 160 |
| Forks | 38 |
| Language | [Verilog](https://repo.masters-masters.com/en/languages/verilog) |
| License | GPL-3.0 |
| Created | 2018 |
| Topics | simd, processor, verilog, processor-design, verilog-project, multiplier, adder, instruction-set-architecture, cadence-virtuoso, cpu |
| Tier | [Prototype (100 to 249 ★)](https://repo.masters-masters.com/en/ranks/rush) |
| View on GitHub | [zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial](https://github.com/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial) |

## Repository

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the oper…

The tier for repos with 100 to 249 ★. Published odds per card pulled: 70%. Rarity: Common.

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Data: GitHub · Illustration drawn by RepoMasters from the repo’s ID and its language color.