# Dépôts SystemVerilog, page 2 [Accueil](https://repo.masters-masters.com/) › [Langages](https://repo.masters-masters.com/languages) › [SystemVerilog](https://repo.masters-masters.com/languages/systemverilog) Les 157 dépôts SystemVerilog open source de RepoMasters, du plus étoilé au moins étoilé : étoiles GitHub, rang et carte à collectionner de chacun. Page 2 sur 6 ## Dépôts SystemVerilog, page 2 157 dépôts SystemVerilog au catalogue, du plus étoilé au moins étoilé. - [taichi-ishitani/tvip-axi · ★ 483 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/taichi-ishitani/tvip-axi) - [VerificationExcellence/SystemVerilogReference · ★ 473 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/VerificationExcellence/SystemVerilogReference) - [fpgasystems/Coyote · ★ 469 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/fpgasystems/Coyote) - [RoaLogic/RV12 · ★ 454 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/RoaLogic/RV12) - [WangXuan95/USTC-RVSoC · ★ 442 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/WangXuan95/USTC-RVSoC) - [raulbehl/100DaysOfRTL · ★ 428 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/raulbehl/100DaysOfRTL) - [gtaylormb/opl3\_fpga · ★ 410 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/gtaylormb/opl3_fpga) - [chipsalliance/sv-tests · ★ 406 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/chipsalliance/sv-tests) - [facebookresearch/deepfloat · ★ 401 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/facebookresearch/deepfloat) - [pulp-platform/FlooNoC · ★ 371 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/pulp-platform/FlooNoC) - [MPSU/APS · ★ 362 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/MPSU/APS) - [chipsalliance/Cores-VeeR-EL2 · ★ 349 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/chipsalliance/Cores-VeeR-EL2) - [RHSResearchLLC/NiteFury-and-LiteFury · ★ 337 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/RHSResearchLLC/NiteFury-and-LiteFury) - [pulp-platform/riscv-dbg · ★ 332 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/pulp-platform/riscv-dbg) - [VerificationExcellence/UVMReference · ★ 308 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/VerificationExcellence/UVMReference) - [bespoke-silicon-group/bsg\_manycore · ★ 305 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/bespoke-silicon-group/bsg_manycore) - [pulp-platform/croc · ★ 294 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/pulp-platform/croc) - [veripool/verilog-mode · ★ 293 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/veripool/verilog-mode) - [tymonx/logic · ★ 292 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/tymonx/logic) - [harishsg993010/tiny-NPU · ★ 291 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/harishsg993010/tiny-NPU) - [openhwfoundation/cv32e40x · ★ 289 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/openhwfoundation/cv32e40x) - [chipsalliance/Cores-VeeR-EH2 · ★ 283 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/chipsalliance/Cores-VeeR-EH2) - [intel/fpga-npu · ★ 267 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/intel/fpga-npu) - [mathis-s/SoomRV · ★ 258 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/mathis-s/SoomRV) - [pulp-platform/iDMA · ★ 254 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/pulp-platform/iDMA) - [dpretet/axi-crossbar · ★ 250 · SystemVerilog · Alpha](https://repo.masters-masters.com/repos/dpretet/axi-crossbar) - [ARC-Lab-UF/sv-tutorial · ★ 248 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/ARC-Lab-UF/sv-tutorial) - [apfaudio/eurorack-pmod · ★ 241 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/apfaudio/eurorack-pmod) - [risclite/SuperScalar-RISCV-CPU · ★ 239 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/risclite/SuperScalar-RISCV-CPU) - [zama-ai/hpu\_fpga · ★ 233 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/zama-ai/hpu_fpga) ## Page 2 sur 6 - [Page précédente](https://repo.masters-masters.com/languages/systemverilog) - [Page suivante](https://repo.masters-masters.com/languages/systemverilog?page=3) --- Données : GitHub