# Dépôts SystemVerilog, page 4 [Accueil](https://repo.masters-masters.com/) › [Langages](https://repo.masters-masters.com/languages) › [SystemVerilog](https://repo.masters-masters.com/languages/systemverilog) Les 157 dépôts SystemVerilog open source de RepoMasters, du plus étoilé au moins étoilé : étoiles GitHub, rang et carte à collectionner de chacun. Page 4 sur 6 ## Dépôts SystemVerilog, page 4 157 dépôts SystemVerilog au catalogue, du plus étoilé au moins étoilé. - [munetomo-maruyama/mmRISC-2 · ★ 167 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/munetomo-maruyama/mmRISC-2) - [srg320/Saturn\_MiSTer · ★ 166 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/srg320/Saturn_MiSTer) - [gnodipac886/ViT-FPGA-TPU · ★ 165 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/gnodipac886/ViT-FPGA-TPU) - [GodelMachine/AHB2 · ★ 164 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/GodelMachine/AHB2) - [openhwfoundation/cv32e40s · ★ 163 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/openhwfoundation/cv32e40s) - [Xilinx/open-nic-shell · ★ 161 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/Xilinx/open-nic-shell) - [iammituraj/pequeno\_riscv · ★ 161 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/iammituraj/pequeno_riscv) - [chenyuliu577-cyber/jyd-rv32i-fpga-core · ★ 161 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/chenyuliu577-cyber/jyd-rv32i-fpga-core) - [agalimberti/NoCRouter · ★ 160 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/agalimberti/NoCRouter) - [chipsalliance/caliptra-rtl · ★ 160 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/chipsalliance/caliptra-rtl) - [accellera-official/uvm-core · ★ 156 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/accellera-official/uvm-core) - [Dollbar/Overflow · ★ 154 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/Dollbar/Overflow) - [dshekhalev/FEC · ★ 153 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/dshekhalev/FEC) - [waviousllc/wav-lpddr-hw · ★ 148 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/waviousllc/wav-lpddr-hw) - [WangXuan95/FPGA-SATA-HBA · ★ 148 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/WangXuan95/FPGA-SATA-HBA) - [ic-lab-duth/RISC-V-Vector · ★ 147 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/ic-lab-duth/RISC-V-Vector) - [amd/mini-isp · ★ 147 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/amd/mini-isp) - [zeroasiccorp/wildebeest · ★ 146 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/zeroasiccorp/wildebeest) - [chipsalliance/uvm-verilator · ★ 143 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/chipsalliance/uvm-verilator) - [pulp-platform/register\_interface · ★ 141 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/pulp-platform/register_interface) - [marcoz001/axi-uvm · ★ 140 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/marcoz001/axi-uvm) - [openhwfoundation/cva5 · ★ 140 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/openhwfoundation/cva5) - [MiSTer-devel/C64\_MiSTer · ★ 139 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/MiSTer-devel/C64_MiSTer) - [microsoft/cheriot-ibex · ★ 138 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/microsoft/cheriot-ibex) - [ZcashFoundation/zcash-fpga · ★ 135 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/ZcashFoundation/zcash-fpga) - [lizhirui/AXI-SDCard-High-Speed-Controller · ★ 131 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/lizhirui/AXI-SDCard-High-Speed-Controller) - [KastnerRG/cgra4ml · ★ 129 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/KastnerRG/cgra4ml) - [agg23/analogue-pocket-utils · ★ 127 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/agg23/analogue-pocket-utils) - [krikzz/edn8-pro-pub · ★ 126 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/krikzz/edn8-pro-pub) - [pulp-platform/redmule · ★ 126 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/pulp-platform/redmule) ## Page 4 sur 6 - [Page précédente](https://repo.masters-masters.com/languages/systemverilog?page=3) - [Page suivante](https://repo.masters-masters.com/languages/systemverilog?page=5) --- Données : GitHub