# Dépôts SystemVerilog, page 5 [Accueil](https://repo.masters-masters.com/) › [Langages](https://repo.masters-masters.com/languages) › [SystemVerilog](https://repo.masters-masters.com/languages/systemverilog) Les 157 dépôts SystemVerilog open source de RepoMasters, du plus étoilé au moins étoilé : étoiles GitHub, rang et carte à collectionner de chacun. Page 5 sur 6 ## Dépôts SystemVerilog, page 5 157 dépôts SystemVerilog au catalogue, du plus étoilé au moins étoilé. - [bsc-loca/sauria · ★ 125 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/bsc-loca/sauria) - [nelsoncsc/ISP\_UVM · ★ 124 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/nelsoncsc/ISP_UVM) - [lowRISC/muntjac · ★ 124 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/lowRISC/muntjac) - [openhwfoundation/cv-hpdcache · ★ 124 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/openhwfoundation/cv-hpdcache) - [meiniKi/FazyRV · ★ 124 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/meiniKi/FazyRV) - [pulp-platform/pulp\_cluster · ★ 123 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/pulp-platform/pulp_cluster) - [RC4ML/Shuhai · ★ 123 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/RC4ML/Shuhai) - [zero-day-labs/riscv-iommu · ★ 122 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/zero-day-labs/riscv-iommu) - [daglem/reDIP-SID · ★ 121 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/daglem/reDIP-SID) - [Siddhi-95/AHB-to-APB-Bridge-Verification · ★ 121 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/Siddhi-95/AHB-to-APB-Bridge-Verification) - [krikzz/mega-ed-pub · ★ 120 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/krikzz/mega-ed-pub) - [StefanSredojevic/Deep-Neural-Network-Hardware-Accelerator · ★ 117 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/StefanSredojevic/Deep-Neural-Network-Hardware-Accelerator) - [chili-chips-ba/openCologne-PCIE · ★ 116 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/chili-chips-ba/openCologne-PCIE) - [chili-chips-ba/openPCIE · ★ 114 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/chili-chips-ba/openPCIE) - [nand2mario/z8086 · ★ 114 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/nand2mario/z8086) - [pulp-platform/hero · ★ 113 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/pulp-platform/hero) - [mole99/greyhound-ihp · ★ 112 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/mole99/greyhound-ihp) - [Verdvana/AXI4\_Interconnect · ★ 111 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/Verdvana/AXI4_Interconnect) - [ttchisholm/10g-low-latency-ethernet · ★ 111 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/ttchisholm/10g-low-latency-ethernet) - [RoaLogic/ahb3lite\_interconnect · ★ 110 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/RoaLogic/ahb3lite_interconnect) - [trivialmips/TrivialMIPS · ★ 110 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/trivialmips/TrivialMIPS) - [eliaskousk/parallella-riscv · ★ 109 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/eliaskousk/parallella-riscv) - [mmxsrup/axi4-interface · ★ 109 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/mmxsrup/axi4-interface) - [Weiyet/MakerCode\_RTLChallenge · ★ 109 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/Weiyet/MakerCode_RTLChallenge) - [spcl/pspin · ★ 108 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/spcl/pspin) - [WangXuan95/UH-JLS · ★ 108 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/WangXuan95/UH-JLS) - [chili-chips-ba/openCologne · ★ 108 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/chili-chips-ba/openCologne) - [seabeam/yuu\_ahb · ★ 106 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/seabeam/yuu_ahb) - [gundy/tiny-synth · ★ 105 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/gundy/tiny-synth) - [OPAE/intel-fpga-bbb · ★ 104 · SystemVerilog · Prototype](https://repo.masters-masters.com/repos/OPAE/intel-fpga-bbb) ## Page 5 sur 6 - [Page précédente](https://repo.masters-masters.com/languages/systemverilog?page=4) - [Page suivante](https://repo.masters-masters.com/languages/systemverilog?page=6) --- Données : GitHub