# Dépôts Verilog, page 5

<https://repo.masters-masters.com/languages/verilog?page=5>

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Les 427 dépôts Verilog open source de RepoMasters, du plus étoilé au moins étoilé : étoiles GitHub, rang et carte à collectionner de chacun. Page 5 sur 15

## Dépôts Verilog, page 5

427 dépôts Verilog au catalogue, du plus étoilé au moins étoilé.

- [EttusResearch/fpga · ★ 315 · Verilog · Alpha](https://repo.masters-masters.com/repos/EttusResearch/fpga)
- [lastweek/fpga\_readings · ★ 315 · Verilog · Alpha](https://repo.masters-masters.com/repos/lastweek/fpga_readings)
- [ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA · ★ 314 · Verilog · Alpha](https://repo.masters-masters.com/repos/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA)
- [fromgof/TridentVision · ★ 313 · Verilog · Alpha](https://repo.masters-masters.com/repos/fromgof/TridentVision)
- [Xilinx/libsystemctlm-soc · ★ 312 · Verilog · Alpha](https://repo.masters-masters.com/repos/Xilinx/libsystemctlm-soc)
- [Modos-Labs/Caster · ★ 312 · Verilog · Alpha](https://repo.masters-masters.com/repos/Modos-Labs/Caster)
- [SparcLab/OpenSERDES · ★ 309 · Verilog · Alpha](https://repo.masters-masters.com/repos/SparcLab/OpenSERDES)
- [budude2/openfpga-GBC · ★ 308 · Verilog · Alpha](https://repo.masters-masters.com/repos/budude2/openfpga-GBC)
- [damdoy/ice40\_ultraplus\_examples · ★ 302 · Verilog · Alpha](https://repo.masters-masters.com/repos/damdoy/ice40_ultraplus_examples)
- [efabless/raven-picorv32 · ★ 299 · Verilog · Alpha](https://repo.masters-masters.com/repos/efabless/raven-picorv32)
- [nand2mario/snestang · ★ 298 · Verilog · Alpha](https://repo.masters-masters.com/repos/nand2mario/snestang)
- [wqzustc/High-Performance-Tensor-Processing-Engines · ★ 297 · Verilog · Alpha](https://repo.masters-masters.com/repos/wqzustc/High-Performance-Tensor-Processing-Engines)
- [opencomputeproject/Project-Zipline · ★ 295 · Verilog · Alpha](https://repo.masters-masters.com/repos/opencomputeproject/Project-Zipline)
- [openasic-org/xk265 · ★ 293 · Verilog · Alpha](https://repo.masters-masters.com/repos/openasic-org/xk265)
- [kramble/FPGA-Litecoin-Miner · ★ 292 · Verilog · Alpha](https://repo.masters-masters.com/repos/kramble/FPGA-Litecoin-Miner)
- [chipsalliance/f4pga-examples · ★ 290 · Verilog · Alpha](https://repo.masters-masters.com/repos/chipsalliance/f4pga-examples)
- [ultraembedded/core\_jpeg · ★ 283 · Verilog · Alpha](https://repo.masters-masters.com/repos/ultraembedded/core_jpeg)
- [GideonZ/1541ultimate · ★ 277 · Verilog · Alpha](https://repo.masters-masters.com/repos/GideonZ/1541ultimate)
- [hamsternz/DisplayPort\_Verilog · ★ 276 · Verilog · Alpha](https://repo.masters-masters.com/repos/hamsternz/DisplayPort_Verilog)
- [brianbennett/fpga\_nes · ★ 275 · Verilog · Alpha](https://repo.masters-masters.com/repos/brianbennett/fpga_nes)
- [Buck008/Transformer-Accelerator-Based-on-FPGA · ★ 275 · Verilog · Alpha](https://repo.masters-masters.com/repos/Buck008/Transformer-Accelerator-Based-on-FPGA)
- [funningboy/uvm\_axi · ★ 274 · Verilog · Alpha](https://repo.masters-masters.com/repos/funningboy/uvm_axi)
- [lsils/benchmarks · ★ 273 · Verilog · Alpha](https://repo.masters-masters.com/repos/lsils/benchmarks)
- [projf/display\_controller · ★ 271 · Verilog · Alpha](https://repo.masters-masters.com/repos/projf/display_controller)
- [MiSTle-Dev/NanoMig · ★ 270 · Verilog · Alpha](https://repo.masters-masters.com/repos/MiSTle-Dev/NanoMig)
- [geohot/twitchcore · ★ 267 · Verilog · Alpha](https://repo.masters-masters.com/repos/geohot/twitchcore)
- [lirui-shanghaitech/CNN-Accelerator-VLSI · ★ 267 · Verilog · Alpha](https://repo.masters-masters.com/repos/lirui-shanghaitech/CNN-Accelerator-VLSI)
- [KULeuven-COSIC/SCALE-MAMBA · ★ 264 · Verilog · Alpha](https://repo.masters-masters.com/repos/KULeuven-COSIC/SCALE-MAMBA)
- [smunaut/ice40-playground · ★ 262 · Verilog · Alpha](https://repo.masters-masters.com/repos/smunaut/ice40-playground)
- [MiSTle-Dev/MiSTeryNano · ★ 261 · Verilog · Alpha](https://repo.masters-masters.com/repos/MiSTle-Dev/MiSTeryNano)

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Données : GitHub