# Dépôts Verilog, page 6 [Accueil](https://repo.masters-masters.com/) › [Langages](https://repo.masters-masters.com/languages) › [Verilog](https://repo.masters-masters.com/languages/verilog) Les 427 dépôts Verilog open source de RepoMasters, du plus étoilé au moins étoilé : étoiles GitHub, rang et carte à collectionner de chacun. Page 6 sur 15 ## Dépôts Verilog, page 6 427 dépôts Verilog au catalogue, du plus étoilé au moins étoilé. - [cliffordwolf/SimpleVOut · ★ 259 · Verilog · Alpha](https://repo.masters-masters.com/repos/cliffordwolf/SimpleVOut) - [RV-BOSC/OpenNoC · ★ 258 · Verilog · Alpha](https://repo.masters-masters.com/repos/RV-BOSC/OpenNoC) - [Mazamars312/Analogue\_Pocket\_Neogeo · ★ 257 · Verilog · Alpha](https://repo.masters-masters.com/repos/Mazamars312/Analogue_Pocket_Neogeo) - [mflowgen/freepdk-45nm · ★ 256 · Verilog · Alpha](https://repo.masters-masters.com/repos/mflowgen/freepdk-45nm) - [The-OpenROAD-Project/RePlAce · ★ 255 · Verilog · Alpha](https://repo.masters-masters.com/repos/The-OpenROAD-Project/RePlAce) - [lauchinyuan/FPGA\_QPSK-modem · ★ 253 · Verilog · Alpha](https://repo.masters-masters.com/repos/lauchinyuan/FPGA_QPSK-modem) - [AniketBadhan/Convolutional-Neural-Network · ★ 249 · Verilog · Prototype](https://repo.masters-masters.com/repos/AniketBadhan/Convolutional-Neural-Network) - [GuoningHuang/FPGA-CNN-accelerator-based-on-systolic-array · ★ 248 · Verilog · Prototype](https://repo.masters-masters.com/repos/GuoningHuang/FPGA-CNN-accelerator-based-on-systolic-array) - [avakar/usbcorev · ★ 244 · Verilog · Prototype](https://repo.masters-masters.com/repos/avakar/usbcorev) - [efabless/caravel\_user\_project · ★ 244 · Verilog · Prototype](https://repo.masters-masters.com/repos/efabless/caravel_user_project) - [hkust-zhiyao/RTLLM · ★ 243 · Verilog · Prototype](https://repo.masters-masters.com/repos/hkust-zhiyao/RTLLM) - [soDLA-publishment/soDLA · ★ 241 · Verilog · Prototype](https://repo.masters-masters.com/repos/soDLA-publishment/soDLA) - [ChFrenkel/ODIN · ★ 241 · Verilog · Prototype](https://repo.masters-masters.com/repos/ChFrenkel/ODIN) - [WangXuan95/FPGA-FixedPoint · ★ 241 · Verilog · Prototype](https://repo.masters-masters.com/repos/WangXuan95/FPGA-FixedPoint) - [chipsalliance/synlig · ★ 237 · Verilog · Prototype](https://repo.masters-masters.com/repos/chipsalliance/synlig) - [snbk001/Verilog-Design-Examples · ★ 235 · Verilog · Prototype](https://repo.masters-masters.com/repos/snbk001/Verilog-Design-Examples) - [nandland/spi-slave · ★ 234 · Verilog · Prototype](https://repo.masters-masters.com/repos/nandland/spi-slave) - [nonarkitten/amiga\_replacement\_project · ★ 234 · Verilog · Prototype](https://repo.masters-masters.com/repos/nonarkitten/amiga_replacement_project) - [furrtek/SiliconRE · ★ 231 · Verilog · Prototype](https://repo.masters-masters.com/repos/furrtek/SiliconRE) - [gsmecher/minimax · ★ 231 · Verilog · Prototype](https://repo.masters-masters.com/repos/gsmecher/minimax) - [cameronshinn/tiny-tpu · ★ 230 · Verilog · Prototype](https://repo.masters-masters.com/repos/cameronshinn/tiny-tpu) - [Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step · ★ 229 · Verilog · Prototype](https://repo.masters-masters.com/repos/Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step) - [WangXuan95/FPGA-DDR-SDRAM · ★ 224 · Verilog · Prototype](https://repo.masters-masters.com/repos/WangXuan95/FPGA-DDR-SDRAM) - [emu-russia/breaks · ★ 223 · Verilog · Prototype](https://repo.masters-masters.com/repos/emu-russia/breaks) - [YosysHQ/riscv-formal · ★ 223 · Verilog · Prototype](https://repo.masters-masters.com/repos/YosysHQ/riscv-formal) - [adamgallas/llama-fpga · ★ 223 · Verilog · Prototype](https://repo.masters-masters.com/repos/adamgallas/llama-fpga) - [wuxx/icesugar-pro · ★ 222 · Verilog · Prototype](https://repo.masters-masters.com/repos/wuxx/icesugar-pro) - [ShawnHymel/introduction-to-fpga · ★ 219 · Verilog · Prototype](https://repo.masters-masters.com/repos/ShawnHymel/introduction-to-fpga) - [WalkerLau/DetectHumanFaces · ★ 217 · Verilog · Prototype](https://repo.masters-masters.com/repos/WalkerLau/DetectHumanFaces) - [eminfedar/fedar-f1-rv64im · ★ 215 · Verilog · Prototype](https://repo.masters-masters.com/repos/eminfedar/fedar-f1-rv64im) ## Page 6 sur 15 - [Page précédente](https://repo.masters-masters.com/languages/verilog?page=5) - [Page suivante](https://repo.masters-masters.com/languages/verilog?page=7) --- Données : GitHub