# Dépôts Verilog, page 7 [Accueil](https://repo.masters-masters.com/) › [Langages](https://repo.masters-masters.com/languages) › [Verilog](https://repo.masters-masters.com/languages/verilog) Les 427 dépôts Verilog open source de RepoMasters, du plus étoilé au moins étoilé : étoiles GitHub, rang et carte à collectionner de chacun. Page 7 sur 15 ## Dépôts Verilog, page 7 427 dépôts Verilog au catalogue, du plus étoilé au moins étoilé. - [cucapra/filament · ★ 215 · Verilog · Prototype](https://repo.masters-masters.com/repos/cucapra/filament) - [MIPSfpga/schoolMIPS · ★ 214 · Verilog · Prototype](https://repo.masters-masters.com/repos/MIPSfpga/schoolMIPS) - [mirkat1206/2021\_Spring\_NCTU\_ICLAB · ★ 214 · Verilog · Prototype](https://repo.masters-masters.com/repos/mirkat1206/2021_Spring_NCTU_ICLAB) - [ultraembedded/riscv\_soc · ★ 213 · Verilog · Prototype](https://repo.masters-masters.com/repos/ultraembedded/riscv_soc) - [zach0zhang/Single\_instruction\_cycle\_OpenMIPS · ★ 210 · Verilog · Prototype](https://repo.masters-masters.com/repos/zach0zhang/Single_instruction_cycle_OpenMIPS) - [risclite/R8051 · ★ 209 · Verilog · Prototype](https://repo.masters-masters.com/repos/risclite/R8051) - [Juniper/open-register-design-tool · ★ 209 · Verilog · Prototype](https://repo.masters-masters.com/repos/Juniper/open-register-design-tool) - [strigeus/fpganes · ★ 208 · Verilog · Prototype](https://repo.masters-masters.com/repos/strigeus/fpganes) - [randyrossi/vicii-kawari · ★ 205 · Verilog · Prototype](https://repo.masters-masters.com/repos/randyrossi/vicii-kawari) - [Lichee-Pi/Tang\_E203\_Mini · ★ 204 · Verilog · Prototype](https://repo.masters-masters.com/repos/Lichee-Pi/Tang_E203_Mini) - [jamieiles/uart · ★ 203 · Verilog · Prototype](https://repo.masters-masters.com/repos/jamieiles/uart) - [rafaelcalcada/rvx · ★ 203 · Verilog · Prototype](https://repo.masters-masters.com/repos/rafaelcalcada/rvx) - [AngeloJacobo/FPGA\_Book\_Experiments · ★ 203 · Verilog · Prototype](https://repo.masters-masters.com/repos/AngeloJacobo/FPGA_Book_Experiments) - [taoyilee/clacc · ★ 202 · Verilog · Prototype](https://repo.masters-masters.com/repos/taoyilee/clacc) - [pwmarcz/fpga-chip8 · ★ 202 · Verilog · Prototype](https://repo.masters-masters.com/repos/pwmarcz/fpga-chip8) - [XueTianyu24/cnn\_accelerator · ★ 202 · Verilog · Prototype](https://repo.masters-masters.com/repos/XueTianyu24/cnn_accelerator) - [tinyfpga/TinyFPGA-B-Series · ★ 201 · Verilog · Prototype](https://repo.masters-masters.com/repos/tinyfpga/TinyFPGA-B-Series) - [sumanth-kalluri/cnn\_hardware\_acclerator\_for\_fpga · ★ 199 · Verilog · Prototype](https://repo.masters-masters.com/repos/sumanth-kalluri/cnn_hardware_acclerator_for_fpga) - [benreynwar/fft-dit-fpga · ★ 198 · Verilog · Prototype](https://repo.masters-masters.com/repos/benreynwar/fft-dit-fpga) - [ben-marshall/uart · ★ 198 · Verilog · Prototype](https://repo.masters-masters.com/repos/ben-marshall/uart) - [thedatabusdotio/fpga-ml-accelerator · ★ 198 · Verilog · Prototype](https://repo.masters-masters.com/repos/thedatabusdotio/fpga-ml-accelerator) - [rejunity/tiny-asic-1\_58bit-matrix-mul · ★ 197 · Verilog · Prototype](https://repo.masters-masters.com/repos/rejunity/tiny-asic-1_58bit-matrix-mul) - [hrvach/fpg1 · ★ 195 · Verilog · Prototype](https://repo.masters-masters.com/repos/hrvach/fpg1) - [ulixxe/usb\_cdc · ★ 194 · Verilog · Prototype](https://repo.masters-masters.com/repos/ulixxe/usb_cdc) - [muditbhargava66/High-Frequency-Trading-FPGA-System · ★ 194 · Verilog · Prototype](https://repo.masters-masters.com/repos/muditbhargava66/High-Frequency-Trading-FPGA-System) - [FPGADude/Digital-Design · ★ 193 · Verilog · Prototype](https://repo.masters-masters.com/repos/FPGADude/Digital-Design) - [bluespec/Toooba · ★ 192 · Verilog · Prototype](https://repo.masters-masters.com/repos/bluespec/Toooba) - [MiSTer-devel/Minimig-AGA\_MiSTer · ★ 191 · Verilog · Prototype](https://repo.masters-masters.com/repos/MiSTer-devel/Minimig-AGA_MiSTer) - [ZFTurbo/MobileNet-in-FPGA · ★ 191 · Verilog · Prototype](https://repo.masters-masters.com/repos/ZFTurbo/MobileNet-in-FPGA) - [FPGAwars/FPGA-peripherals · ★ 189 · Verilog · Prototype](https://repo.masters-masters.com/repos/FPGAwars/FPGA-peripherals) ## Page 7 sur 15 - [Page précédente](https://repo.masters-masters.com/languages/verilog?page=6) - [Page suivante](https://repo.masters-masters.com/languages/verilog?page=8) --- Données : GitHub