# Dépôts Verilog, page 9 [Accueil](https://repo.masters-masters.com/) › [Langages](https://repo.masters-masters.com/languages) › [Verilog](https://repo.masters-masters.com/languages/verilog) Les 427 dépôts Verilog open source de RepoMasters, du plus étoilé au moins étoilé : étoiles GitHub, rang et carte à collectionner de chacun. Page 9 sur 15 ## Dépôts Verilog, page 9 427 dépôts Verilog au catalogue, du plus étoilé au moins étoilé. - [kunalg123/vsdflow · ★ 170 · Verilog · Prototype](https://repo.masters-masters.com/repos/kunalg123/vsdflow) - [im-tomu/fomu-workshop · ★ 170 · Verilog · Prototype](https://repo.masters-masters.com/repos/im-tomu/fomu-workshop) - [liuqdev/8-bits-RISC-CPU-Verilog · ★ 169 · Verilog · Prototype](https://repo.masters-masters.com/repos/liuqdev/8-bits-RISC-CPU-Verilog) - [dan-rodrigues/icestation-32 · ★ 169 · Verilog · Prototype](https://repo.masters-masters.com/repos/dan-rodrigues/icestation-32) - [padhi499/Image-Classification-using-CNN-on-FPGA · ★ 169 · Verilog · Prototype](https://repo.masters-masters.com/repos/padhi499/Image-Classification-using-CNN-on-FPGA) - [keplertech/naja · ★ 169 · Verilog · Prototype](https://repo.masters-masters.com/repos/keplertech/naja) - [andres-mancera/ethernet\_10ge\_mac\_SV\_UVM\_tb · ★ 168 · Verilog · Prototype](https://repo.masters-masters.com/repos/andres-mancera/ethernet_10ge_mac_SV_UVM_tb) - [Edragon/FPGA\_DOCS · ★ 168 · Verilog · Prototype](https://repo.masters-masters.com/repos/Edragon/FPGA_DOCS) - [ExcessiveMotion/controller-software · ★ 168 · Verilog · Prototype](https://repo.masters-masters.com/repos/ExcessiveMotion/controller-software) - [alan4186/Hardware-CNN · ★ 167 · Verilog · Prototype](https://repo.masters-masters.com/repos/alan4186/Hardware-CNN) - [chriz2600/DreamcastHDMI · ★ 167 · Verilog · Prototype](https://repo.masters-masters.com/repos/chriz2600/DreamcastHDMI) - [lisper/cpus-caddr · ★ 166 · Verilog · Prototype](https://repo.masters-masters.com/repos/lisper/cpus-caddr) - [onchipuis/mriscv · ★ 166 · Verilog · Prototype](https://repo.masters-masters.com/repos/onchipuis/mriscv) - [regymm/quasiSoC · ★ 166 · Verilog · Prototype](https://repo.masters-masters.com/repos/regymm/quasiSoC) - [drandyhaas/Haasoscope · ★ 165 · Verilog · Prototype](https://repo.masters-masters.com/repos/drandyhaas/Haasoscope) - [mhyousefi/MIPS-pipeline-processor · ★ 164 · Verilog · Prototype](https://repo.masters-masters.com/repos/mhyousefi/MIPS-pipeline-processor) - [ConstStrings/GoWinSDR · ★ 164 · Verilog · Prototype](https://repo.masters-masters.com/repos/ConstStrings/GoWinSDR) - [icebreaker-fpga/icebreaker-verilog-examples · ★ 162 · Verilog · Prototype](https://repo.masters-masters.com/repos/icebreaker-fpga/icebreaker-verilog-examples) - [leo47007/TPU-Tensor-Processing-Unit · ★ 162 · Verilog · Prototype](https://repo.masters-masters.com/repos/leo47007/TPU-Tensor-Processing-Unit) - [WangXuan95/FPGA-Gzip-compressor · ★ 162 · Verilog · Prototype](https://repo.masters-masters.com/repos/WangXuan95/FPGA-Gzip-compressor) - [TimRudy/ice-chips-verilog · ★ 160 · Verilog · Prototype](https://repo.masters-masters.com/repos/TimRudy/ice-chips-verilog) - [zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial · ★ 160 · Verilog · Prototype](https://repo.masters-masters.com/repos/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial) - [KASIRGA-KIZIL/tekno-kizil · ★ 160 · Verilog · Prototype](https://repo.masters-masters.com/repos/KASIRGA-KIZIL/tekno-kizil) - [Kyrie-T/HPMM · ★ 160 · Verilog · Prototype](https://repo.masters-masters.com/repos/Kyrie-T/HPMM) - [MasLiang/CNN-On-FPGA · ★ 159 · Verilog · Prototype](https://repo.masters-masters.com/repos/MasLiang/CNN-On-FPGA) - [dom0ng/pcileech-wifi-v2 · ★ 158 · Verilog · Prototype](https://repo.masters-masters.com/repos/dom0ng/pcileech-wifi-v2) - [kevin861222/NYCU-ICLAB-2024-Spring · ★ 158 · Verilog · Prototype](https://repo.masters-masters.com/repos/kevin861222/NYCU-ICLAB-2024-Spring) - [lekgolo167/enxor-logic-analyzer · ★ 157 · Verilog · Prototype](https://repo.masters-masters.com/repos/lekgolo167/enxor-logic-analyzer) - [BoooC/CNN-Accelerator-Based-on-Eyeriss-v2 · ★ 157 · Verilog · Prototype](https://repo.masters-masters.com/repos/BoooC/CNN-Accelerator-Based-on-Eyeriss-v2) - [m-labs/milkymist · ★ 155 · Verilog · Prototype](https://repo.masters-masters.com/repos/m-labs/milkymist) ## Page 9 sur 15 - [Page précédente](https://repo.masters-masters.com/languages/verilog?page=8) - [Page suivante](https://repo.masters-masters.com/languages/verilog?page=10) --- Données : GitHub