PrototypeCommune
lakshmi-sathi/avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
- Propriétaire
- lakshmi-sathi (compte personnel)
- Étoiles
- Étoiles : 126
- Forks
- Forks : 40
- Langage
- Sans langage
- Licence
- GPL-2.0
- Création
- 2020
- Sujets
- pllclock-multiplierintellectual-propertyanalog-circuitphase-detectorcharge-pumprtl2gdsmanufacturableicasic
- Rang
- Prototype (100 à 249 ★) Ce que veut dire ce rang