PrototypeCommune
mirseo/JSilicon
JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.
- Propriétaire
- mirseo (compte personnel)
- Étoiles
- Étoiles : 101
- Forks
- Forks : 10
- Langage
- SystemVerilog
- Licence
- Apache-2.0
- Création
- 2025
- Sujets
- aluasicchip-designfinite-state-machinertlrtl-designverilogcontrol-logicdigital-designsopen-source-hardware
- Rang
- Prototype (100 à 249 ★) Ce que veut dire ce rang
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