PrototypeCommon
RISC-KC/basic_rv32s
🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.
- Owner
- RISC-KC (organization)
- Stars
- Stars: 113
- Forks
- Forks: 11
- Language
- Verilog
- License
- MIT
- Created
- 2024
- Topics
- computer-architecturecomputer-sciencecpudhrystonefpgahdlprocessorprocessor-designrisc-vriscv
- Tier
- Prototype (100 to 249 ★) What this tier means
Nearby in Verilog
All Verilog repos- MIPSfpga/mipsfpga-plusStars: 113VerilogPrototype
- ispras/hdl-benchmarksStars: 113VerilogPrototype
- lucysrausch/colorlight-led-cubeStars: 113VerilogPrototype