BetaRare
aolofsson/oh
Verilog library for ASIC and FPGA designers
Archived: this repository is read-only
- Owner
- aolofsson (personal account)
- Stars
- Stars: 1,440
- Forks
- Forks: 304
- Language
- Verilog
- License
- MIT
- Created
- 2015
- Tier
- Beta (700 to 1,999 ★) What this tier means
More repos by aolofsson
All 4 repos by aolofsson- aolofsson/awesome-opensource-hardwareStars: 2,456PythonRC
- aolofsson/awesome-semiconductor-startupsStars: 786PythonBeta
- aolofsson/awesome-opensource-hardware-reposStars: 365PythonAlpha
Nearby in Verilog
All Verilog repos- alexforencich/verilog-pcieStars: 1,675VerilogBeta
- ZipCPU/zipcpuStars: 1,597VerilogBeta
- XUANTIE-RV/openc910Stars: 1,491VerilogBeta
- VerticalResearchGroup/miaowStars: 1,431VerilogBeta
- tiny-tpu-v2/tiny-tpuStars: 1,413VerilogBeta
- ultraembedded/biriscvStars: 1,329VerilogBeta